Ultrathin New Dielectric Interlayer Layer - Enhancer for TEOS-TEOS Bond Strength at Low Thermal Budget for C2W and W2W Bonding Applications

Three-dimensional integrated circuit (3D IC) packaging is becoming promising for automation and high-performance computing applications. High-density fine-pitch metal/dielectric hybrid bonding is a key requirement for its realization. As dielectric bonding plays a significant role, there is a quest for new dielectric materials, with a focus on achieving high bond strengths at lower thermal budgets. However, while replacing conventional dielectrics with new ones, there may be integration changes resulting in more process complexities. In this context, we propose a new method of integrating new dielectrics with flows that are damascene compatible. In addition, the study demonstrates wafer bonding for various dielectric combinations and the resultant bond strength at the thermal budget as low as 230 °C for 2 h. Optimal dielectric bonding stack combinations have been demonstrated for future integration. This process integration will be helpful for fine-pitch high-density hybrid bonding chip-to-chip (C2C), chip-to-wafer (C2W), and wafer-to-wafer (W2W) integration approaches.