Effect of Scribe Line Metal Layout on Wafer Saw Top Edge Chipping for Silicon Power Devices

We report on edge chipping from wafer saw during development of a 0.35 μm BCD technology. It was initially thought that the edge chipping was due to thick Cu and Al layers used for power distribution and the bond pads, respectively. However, it was finally determined that the edge chipping was due to 50x50 μm² wide W filled regions ("Tox Boxes"), used to measure oxide interlayer oxide thickness after CMP. Edge chipping was greatly reduced by eliminating the wide W-filled Tox Boxes in the scribe.