Evaluation of Low Temperature Inorganic Dielectric Materials for Hybrid Bonding Applications

High-bandwidth memory (HBM) market is witnessing huge demand for high performance computing. Vertical/3D stacking of memory chips using hybrid bonding is a widely explored technology for HBMs. For chip stacking, hybrid bond pads need to be fabricated on both sides of the wafer. The backside fabrication of the wafer is done using temporary bonding-debonding (TBDB) process and thus requires post-TBDB dielectric materials deposition temperature to be kept < 200 °C to meet the thermal budget of the temporary bonded glue material. In this paper, two dielectric materials were evaluated on the wafer backside, i.e., low temperature tetraethyl orthosilicate (TEOS) and Silicon carbon nitride (SiCN), both deposited below 200 °C. The fabrication of hybrid bond pads was done using standard Cu damascene fabrication flow. The surface roughness of the dielectric and Cu pad dishing after the chemical mechanical planarization (CMP) process are critical factors for obtaining a good bonding interface. Atomic force microscopy (AFM) analysis was done to measure the roughness and dishing profile. Chip to wafer hybrid bonding evaluation was performed and four chip stacking was demonstrated using SiCN dielectric. Electrical test, and cross-sectional scanning electron microscopy (XSEM) analysis were performed to monitor the bond quality.