A Novel Packaging Solution for Photonic Engine Application

Silicon photonic is a very promising solution to meet the dramatical increase of bandwidth and the ultra-low power consumption demands for data centers and high-performance computing. One of the challenges on realization of final product is the packaging which integrate both electronics integrated circuits (EICs) and the photonics integrated circuits (PICs). A careful packaging solution should be developed to handle higher bandwidth at a cost of lower power consumption, or improper solution can negate all the possible benefit of silicon photonic. In this paper, we suggest a novel packaging solution by the combined method of flip-chip and wire-bonding to realize 400G data rate photonic engine.