Influence of Parasitic Power Loop Inductance on Switch Performance in GaN HEMT

Gallium nitride high electron-mobility transistors (GaN HEMT) have attracted great interest in half-bridge circuits due to their excellent high-frequency characteristics. To embedded packaging these advantages, with low-parasitic inductance, however, a low-parasitic PCB layout for is required to fully utilize inductance. In this article, we study the method for reducing the power loop inductance and analyze its influence on the switching performance. Six PCB layout structures of power loop based on GS66508T were designed and experimentally fabricated, and the parasitic inductances were extracted and analyzed. The results show that the "I" type layout of vertical structure has the lowest power loop inductance of 2.38 nH. The turn-on ΔV was calculated to demonstrate that the switching loss increases with the decrease of the power loop inductance. It is necessary to minimize the parasitic inductance of the power loop to reduce voltage overshoot in PCB design.