A High Holding Voltage Diode-Triggered SCR for Low-Voltage ESD Application

This paper presents the effect of the emitter area on the holding voltage of a diode-triggered siliconcontrolled rectifier (DTSCR). By reducing the emitter area of the DTSCR, the current gain of the parasitic BJT is reduced, thus both the holding voltage (V
h
) and the holding current (I
h
) can be improved. The prototype DTSCR is fabricated in a 40nm CMOS process. Both simulation and measurement results show that reducing the emitter area (from 100 µm
²
to 50 µm
²
) increases 7.2 % of V
h
and 5.8 % of I
h.