Compact Characteristic Modeling of Cryo-CMOS Transistors Based on Commercial Process Design Kit

A compact characteristic modeling method for CMOS transistors in cryogenic conditions is proposed, based on a commercial process design kit (PDK). Among the various characteristic changes of cryogenic CMOS (cryo-CMOS) transistors, the increases in threshold voltage and mobility are emulated by adjusting only two parameter values, VFBO and STBETO in the PSP model. The proposed modeling method can simplify the modification of an existing PDK based on the PSP model for cryo-CMOS circuit design. To validate the proposed modeling method, a dynamic comparator is designed and evaluated using the standard PDK of 28-nm bulk CMOS technology.