Targeting different defect-oriented fault models in IC testing: an experimental approach

In the field of integrated circuit (IC) testing, the detection of defects is crucial to ensure the reliability and functionality of the final product. Among the variety of fault models that can be used to target the many possible defects in a circuit, delay faults (transition and path delay) have been used for many years. Lately, cell-aware testing (CAT) has been introduced as a different approach that aims to improve the detection of internal defects of standard cells: it involves using specific patterns to detect faults that could not be detected by common fault models (e.g., stuck-at and transition delay fault models). Both delay and cell-aware faults can be caused by several factors, such as manufacturing defects, environmental conditions, and aging effects. In this paper, we investigate the application of test patterns generated with the transition and path delay fault models in comparison with others developed with the cell-aware approach, in terms of fault coverage, pattern count and test generation time. Overall, the study shows that the combination of the path delay fault model and cell-aware testing can lead to improved fault coverage and lower test. The experimental results are presented over a wide range of open-source benchmarks and on a RISC-V design using a proprietary industrial technology library.