Guarded Low Power Hardware Implementations

In the most hardware implementations, the objectives are improving the performance or reducing the power dissipation. Here, anyone can be achieved at the cost of others. This paper proposes guarded low power hardware implementations, where the switching power dissipation is reduced by guarding the non-active portions of the circuit. We have implemented this guarded low power technique to 8-bit Wallace tree multiplier and 32-bit buffered $4 \times 4$-cross bar switch using ZYNQ7000 FPGA with Xilinx Vivado. The synthesis results prove that our proposed low power designs achieve considerable reduction in the dynamic power than the existing techniques. For example, the proposed low power technique with $8 \times 8$-bit Wallace tree multiplier achieves 20% of reduction of the dynamic power than the conventional synchronous design. Similarly, the proposed low power technique with 32 -bit buffered $4 \times 4$-cross bar switch achieves 25% of reduction of the dynamic power than the conventional buffered design [10].