10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm

The most common approach for designing a low-jitter PLL is to use a narrow loop bandwidth (BW) to naturally suppress in-band noise, including quantization noise (Q-noise). In this method, the design of a low phase-noise (PN) LC VCO is vital since its PN, which is barely suppressed by the loop, ultimately determines the rms jitter of the output signal, S
OUT
. Recently, multicore LC VCOs [1, 2] were presented to lower the PN by surpassing the theoretical limit of typical single-core VCOs. However, this advantage comes at the cost of larger silicon area and higher fabrication expenses. An alternative solution to generating low-jitter signals while utilizing minimal silicon area is the design of a digital PLL (DPLL) that uses the combination of a compactly integrated LC VCO and a wide BW that can sufficiently suppress the poor PN of the VCO. The success of this approach heavily relies on accurately removing in-band-noise sources. A DTC is commonly used before the TDC to cancel the Q-noise of the ΔΣM [2–4], and a phase selector (PSEL) is used after the MMD to reduce the DTC range and its thermal noise [2]. The essential part of these jitter-reduction techniques is a background multivariable calibration (MVC), which continuously compensates for the non-linearities (NLs) of the circuits. Due to its low hardware (HW) complexity [2–5], the least-mean-squares (LMS) algorithm has been the sole option for on-chip calibration. However, the critical problem with it is that the overall convergence time grows exponentially as the number of variables increases, easily exceeding hundreds of microseconds [3].