2.1 A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC

Built for upcoming flagship smartphones, this paper describes a new tri-gear CPU subsystem that represents a paradigm shift in mobile SoCs. While tri-gear CPU subsystems have been published [1] [2], this work is the first publication to feature Out-of-Order (OoO) CPUs in all three gears of the cluster. Implemented in a 4nm CMOS process, four OoO High Efficiency (HE) cores are complemented by three Balanced Performance (BP) cores, and a single High Performance (HP) core. Critically, full hardware DVFS control is achieved through enhancements to the DVFS control mechanism of prior work [3]. By utilizing an automatic dual-rail equalizer for SRAM supplies and a new High-Bandwidth Voltage Controller (HBVC) for core supplies, all software dependency on power supply sequencing is eliminated. A power benefit is realized through faster response time and by leveraging a power saving mode in the PMIC. Full-CMOS single-rail memories for frequently accessed first-level caches (L1${\$}$) deliver significant power savings, while layout techniques for reducing standard cell resistance and capacitance in mid-level layers improve maximum clock frequency. A die photograph is shown in Fig. 2.1.7 and the single-thread power and performance comparison is summarized in Fig. 2.1.1.