9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm

Ring amplifiers [1–9] are promising energy-efficient alternatives to OTAs for switched-capacitor residue amplifiers. A ring amplifier is essentially a cascaded multi-stage inverter-based amplifier that is stabilized by a dominant pole at the last stage output with sub-threshold biasing. Although ring amplifiers offer slew-based charging, wide output swing, and high gain, the last stage biasing is still problematic considering mismatch and PVT variation. The self-biased ring amplifier [1] (Fig. 9.2.1 (a)) biases the last stage with a resistor placed in the $2^{\text {nd }}$-stage. While this IR-drop-based biasing effectively tracks first-order PVT variation and demonstrates a reasonable tolerance to VT variation [2], covering a wide range of variations with a fixed resistance is challenging due to the nonlinear relationship between $\left(V_{G S}-V_{T H}\right)$ and $I_{D S}$. The fixed resistor is replaced with a CMOS resistor [3–6] (Fig. 9.2.1 (b)) to provide flexibility in the last stage biasing using bias voltages $V_{B H}$ and $V_{B L}$. However, generating the optimum bias voltages without external tuning requires complex off-chip background digital calibration with ring amplifier behavior monitoring circuits $[4,5]$ or dither-injection-based histogram analysis [6]. The conventional class-AB amplifier bias circuit is adopted in [7, 8] (Fig. 9.2.1 (c)) for the optimum bias voltage generation without calibration. In addition, the $2^{\text {nd }}$-stages are also biased using the current mirrors with AC-coupled capacitors. Although this current mirror-based biasing offers stable performance across PVT variation, mismatch remains a concern. Mismatch is particularly challenging for energy efficient ring amplifiers because, unlike conventional class-AB amplifiers, it is desirable to design the last two stages with small-sized transistors for wide internal node bandwidth with low quiescent current by reducing the capacitive loading of the preceding stages. We introduce a dynamically biased ring amplifier to provide mismatch and PVT variation tolerance, and apply it in a 12b $400 \mathrm{MS} / \mathrm{s}$ pipelined-SAR ADC, achieving Walden and Schreier FoMs of $3.8 \mathrm{fJ} / \mathrm{c}$. s. and $174.2 \mathrm{~dB}$, respectively, without any ring amplifier bias or residue gain calibration.