3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS

The front-end amplifier typically determines the noise level of a sensor system. Therefore, a highly power-efficient amplifier plays a critical role in Internet-of-Things (IoT) applications with stringent power constraints and small input amplitude [1, 2]. Due to the physical limitation between transconductance and current consumption, there exists a severe power-noise trade-off. Several approaches have been proposed to address this issue. Inverter-stacking topologies in [3] concentrate on boosting the current efficiency $\mathrm{g}_{\mathrm{m}} / \mathrm{I}_{\mathrm{d}}$, achieving high noise-efficiency factors (NEF) through current-reuse techniques. However, the increased supply voltages result in worsened power-efficiency factors (PEF). The tail-less inverter-stacking amplifier in [4] enables low supply voltage operation, but the tail-less input stage makes it susceptible to common-mode and supply fluctuations. The amplifier in [5] operates its input stage and following stages under 0.2V and 0.8V separately. With a low-supply-voltage input stage, the power efficiency is improved but at the cost of an extra DC-DC converter. The recently proposed passive discrete-time amplifiers (DTA) achieve a PEF as low as 0.1 [6], but the sampling process introduces aliasing problems, and using an anti-aliasing filter can bring about additional noise and power-related issues.