2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications

To enable emerging mission-critical applications, e.g., healthcare monitoring, remote surgery, and autonomous driving, 5G/6G ultra-reliable low-latency communication (URLLC) devices demand the concurrent fulfillment of ultra-reliability, low-latency, and low-power communications, particularly in short data transmissions as depicted in Fig. 2.8.1. However, the existing short-length forward error-correction (FEC) solutions for URLLC devices cannot meet all the challenging requirements at the same time. The recent short block-length and low-rate block orthogonal sparse superposition (BOSS) code [1] has been proposed as one of the promising next-generation FEC candidates to support all the URLLC features with its low latency and strong reliability. This work presents an integrated BOSS decoder as an URLLC FEC solution by fully capitalizing on the BOSS code’s robust error correction and low latency. Our design achieves enhanced area and energy efficiencies at a low area cost, outperforming the state-of-the-art URLLC FEC designs [2–6].