15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node

For applications where a significant amount of data is processed within a limited area, such as mobile and graphics applications, the demand for higher-density SRAM becomes more evident [1]. As shown in Fig. 15.4.1 (top left), SRAM cell area is progressively decreasing with technology scaling to achieve high-density [2]. However, in sub-5nm technology nodes, shown in Fig. 15.4.1 (top right), the reduction of the interconnect cross-sectional area and decreased electron mobility, due to grain boundary scattering and surface scattering, leads to an exponential increase in interconnect resistance. Despite scaling-driven BL length reduction an exponential increase in interconnect resistance results in an increase in the BL resistance per cell $(\mathrm{R}_{\mathrm{BL} \_ \text {cell }})$, resulting in writability degradation. Figure 15.4.1 (bottom) shows the $\mathrm{R}_{\mathrm{BL} \_ \text {cell }}$ and BL capacitance per cell $(\mathrm{C}_{\mathrm{BL} \_ \text {cell }})$ for recent work using sub-5nm technology nodes. As shown in Fig. 15.4.2, the voltage of BL (or BLB) connected to the selected cell $(\mathrm{V}_{\mathrm{BL} \_ \text {cell }})$ is determined by the voltage dividing characteristic from the cell supply voltage $(\mathrm{V}_{DD_{-}C})$, in the selected cell, to the ground voltage (V
SS
), in write driver (WD), during a write operation. As R
BL
becomes larger, so does $\mathrm{V}_{\mathrm{BL} \_ \text {cell }}$. An increased $\mathrm{V}_{\mathrm{BL} \_ \text {cell }}$ reduces the write current through the pass-gate transistor (PG), resulting in write failures.