13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency

The demand for high-bandwidth data communication in various data-centric applications has increased significantly. It requires many repetitive data transfers between processing units and off-chip memories, owing to the limited memory I/O bandwidth. This results in a deterioration in system throughput and energy efficiency. Therefore, an energy-efficient and high-bandwidth memory interface is required. NRZ signaling [1], [2] is commonly used in memory interfaces; however, it is difficult to increase the I/O bandwidth beyond a certain point owing to on-chip bandwidth limitations. PAM-4 signaling [3], [4] increases the I/O bandwidth by transmitting 2b in 1UI. However, PAM-4 signaling has a reduced signal-to-noise ratio (SNR), which deteriorates further as the power supply voltage is scaled down. PAM-3 signaling [5], [6] can alleviate the above problems because it can achieve better SNR than PAM-4 signaling and a higher I/O bandwidth than NRZ signaling. The proposed transmitter (TX) supports NRZ and PAM-3 modes depending on the operating speed. It uses a 9b/6UI encoded partial data bus inversion (pDBI) transmitted through the DQ lane, achieving a 133% I/O bandwidth/pin efficiency and 19.3% reduction in signaling power, or DBI efficiency. NRZ/PAM-3 ZQ calibration performs a one-and two-point calibration, ensuring a good TX ratio of level mismatch (RLM) in PAM-3 mode.