9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique

The residue amplifier (RA) in a pipelined-SAR ADC eases the noise requirement of the back-end stage, making the architecture energy-efficient. However, to achieve high precision, the RA requires both a substantial gain and a high level of linearity. Conventionally, the requirement is met using a closed-loop amplifier [1– 2]. However, it consumes a significant amount of power to attain a sufficient bandwidth for settling. To address this problem, the open-loop amplifier has been introduced for energy efficiency [3– 4]. Nevertheless, the properties of poor linearity, insufficient gain, and limited output swing restrict its application scenarios. This work presents a 50MS/s pipelined SAR ADC using a cascode capacitively degenerated dynamic amplifier (CCD-DA), which possesses inherent linearity and boosted gain as the residue amplifier. Additionally, a PTAT bias current is employed to ensure PVT robustness. Furthermore, the MSB pre-conversion technique is proposed to further extend the output swing of the dynamic amplifier. The prototype ADC achieves 73.9dB SNDR and 89.4dB SFDR at Nyquist input while consuming only 0.36mW. This corresponds to the best Walden FoM of 1.78fJ/conv.- step and the best Schreier FoM of 182.3dB among the state-of-the-art work compared in Fig 9.4.6 with equivalent or higher sampling rates.