Ultra-Wideband CMOS SOI Switched Delay Line Circulator Using Latticely Coupled Inductor Delay

This article presents a nonmagnetic circulator that realizes nonreciprocity by sequentially switching delay lines, which is fabricated in a 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The electrical length of delay lines is 90° at the switching clock frequency of 1.65 GHz. The proposed circulator is designed differentially to increase the bandwidth as well as power-handling capability. The differential synthetic delay lines can utilize latticely coupled inductors with an optimized winding sequence, resulting in an ultra-wideband. The characteristic impedance of the delay lines is determined by considering the channel resistance of CMOS transistor for a higher isolation. The measured insertion losses of the transmitter (TX) to the antenna (ANT) and ANT to the receiver (RX) are 2.5 and 2.6 dB, respectively. The TX to RX isolation is
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20 dB up to 7 GHz. The circulator demonstrates a TX input power 1-dB compression point (IP textsubscript 1 dB) of 4.7 dBm and ANT input third-order intercept point (IIP3) of 17.2 dBm at 3.5 GHz with 1.65-GHz clock. The achieved highest data rate is 9.8 Gb/s using 128 quadrature amplitude modulation (QAM) with an error vector magnitude (EVM) of 3.9% at a carrier frequency of 2.475 GHz. The measured noise figure (NF) is consistent with the ANT to RX path insertion loss except for the harmonics of the clock frequency. Only the quadrature clock generation circuitry consumes a dc power of 20 mW. The circulator occupies 0.96 mm2, which is comparable to a single-ended version because of the differentially coupled inductors.