Design of a Pixel Readout ASIC Using Super Pixel Circuits With a Built-In LDO Regulator for Hybrid X-Ray Imaging Detectors

A pixel readout application-specific integrated circuit is a key device to construct a hybrid pixel detector for X-ray imaging applications. Voltage drop problems due to parasitic resistance in the power network of the pixel matrix introduces nonuniformity of circuit performance such as dynamic range, gain and noise characteristics among readout pixels. Thus, improving the uniformity of the measured data from each pixel readout circuit is critical for the development of such pixel readout ASIC. This brief presents a novel super pixel circuit topology with a built-in pixelated low-dropout regulator to enhance uniformity. A
$16\times16$
prototype is fabricated with 180nm CMOS process. The die size of the prototype chip is 1.8 mm
$\times2.$
2 mm with a pixel pitch of
$100~\mu \text{m}$
. The dynamic range of input charges is 1 fC
$\sim ~10$
fC. The equivalent noise charge is 200 e-(rms). The power consumption per single pixel with low-dropout regulator in the photon counting mode and energy resolution mode is about
$40~\mu \text{W}$
and
$54~\mu \text{W}$
. The simulated maximum IR drop is only
$80~\mu \text{V}$
. The tested CSA gain variance of the proposed scheme is only 0.379 mV/fC. The measured data indicate that the proposed scheme can well enhance the uniformity of the output data from each pixel readout circuit.