Comparison of Interpolation Scaling Algorithm and Efficient VLSI Design of Win-Scale Interpolation for Run Time Digital Picture Spreading

The rapid expansion of digital display sizes, the clarity of digital image demonstration has increased. Although the computational cost of the win-scale algorithm prevents it from processing in real-time. In this study, we put the win-scale algorithm into an effective VLSI architecture design. This method is suited for digital image display in a range of various sharpness of the image. The Correspondence calculator register, the picture element adjustment unit, the dimension calculation unit, and the accumulating unit make up the heart of the system. The successful development of the speedy VLSI architectonics has been built using our method. The simulation findings show that digital picture spreading for HDTV can be processed in run time by the high-performance image scaling architecture running at frequency 128.37MHz with 18763 total gates in 450x450 micrometer square main size of the wafer.