Performance Analysis for Multi-Level Inverter with Reduced Switch Count Along with PWM Technique and Reduction in Harmonics

This research explores the design of a Multi-Level Inverter (MLI) with a reduced switch count while concurrently enhancing its performance and mitigating harmonic content. The investigation begins with the selection of the Diode-Clamped MLI topology for its inherent advantages in achieving multiple voltage levels with fewer switches. Sinusoidal Pulse Width Modulation (SPWM) techniques are employed to control the output voltage waveform, enabling precise voltage magnitude control. Selective Harmonic Elimination (SHE) strategies are implemented to mitigate harmonic content by selectively eliminating undesirable harmonics, significantly reducing Total Harmonic Distortion (THD). Genetic Algorithm (GA) optimization is utilized to fine-tune modulation indices and switching angles, leading to a substantial reduction in switch count. Experimental validation confirms the feasibility of the design, showcasing reduced switch count, enhanced performance, and minimized harmonic distortion. This research has profound implications for renewable energy integration, electric vehicle charging, industrial motor drives, grid stability, and power quality improvement, promoting sustainability and efficiency across diverse applications. Future directions encompass topology optimization, advanced control algorithms, energy storage integration, and cyber security considerations, ushering in a promising era of innovation in power electronics.