High-Resolution Digital PWM Optimization Method for Critical Path Delay in General FPGA

This paper proposes a high-resolution digital pulse width modulator (DPWM) signal optimization method for the critical path delay based on a field programmable gate array (FPGA), which mainly aims to improve the output regulation accuracy and linearity of the DPWM. This method realizes high-resolution and high-linearity DPWM output by constructing the logical symmetric multiplexer and the synchronous 2-to-1 selector for the critical path, and a simple placement constraint is used to reduce the critical path delay deviation. The high-resolution DPWM signal has the advantages of excellent linearity, easy expansion, and strong versatility, thus especially suitable for power electronic switching converters with high frequency, high accuracy, and high real-time control. The simulation and experimental results show that the DPWM with different FPGA achieves a resolution of 312.5 ps and high linearity, where R2 is up to 0.99999. Finally, the proposed method is verified in a 48 V to 1 V DC/DC converter with a switching frequency of 1 MHz.