Small Area and High Throughput Error Correction Module of STT-MRAM for Object Recognition Systems

This article proposes a novel error correction code (ECC) module designed for future object recognition systems that are expected to utilize spin-transfer torque MRAM (STT-MRAM) for weight data storage. The module focuses on achieving high throughput and a small area while ensuring the integrity of the data. A pipelined high-parallel Bose–Chaudhuri–Hocquenghem (BCH) module is proposed to address the high throughput requirement of the ECC module in STT-MRAM. A 64-parallel linear feedback shift register for the encoder and parallel factor reduced decoder are proposed to optimize the small area requirement, however, maintain the read delay within the nanosecond level. Code length and correction capability of BCH codes are optimized, which are feasible to object recognition systems with high efficiency of memory redundancy and computational complexity. The ECC's correction performance is verified using error maps obtained from practical measurements of real-working STT-MRAM chips fabricated using 37 nm MTJ/40 nm CMOS technologies. The implementation results demonstrate that the proposed ECC module achieved the highest throughput of 64
${bit} \cdot {{f}}_{{clk}}$
and a small area of 18.27K
$\mu {\mathrm{m}}^2$
with a read latency of 5.76 ns. Practical experiments utilized error maps of STT-MRAM and MobileNet weight dataset based on CNN to verify the proposed ECC. Experiment results demonstrated the proposed ECC module achieved no accuracy degradation when the bit error rate of STT-MRAM is under 2×10
^-3
for neural networks.