Low-Power Approximate Multiplier Architecture for Error Resilient Applications

Approximate computing offers a solution since it is a potential technique to improve area, speed, and reduce power in cases when accurate calculation is not expected. In this work, an unsigned approximate multiplier architecture has been presented for error resilient applications. This architecture is divided into three segments: the least significant component remains constant and maintains the same accuracy, the middle portion, which is a partial product, is simplified using or gates, and the error is compensated utilizing an error correction module. According to results of 8-bit multiplier, 30.9% and 35.33% were reduced of power and power-delay products, respectively, compared state-of-the-art designs without sacrificing accuracy. Finally, proposed design is validated using error resilient applications.