High performance low power V/sub T/-wave-pipeline CMOS circuit in PD/SOI technology

Summary form only given. We have presented a V/sub T/-wave-pipeline technique for pseudo-static circuit style. The technique was evaluated using the critical path of a 64 bit carry-look-ahead adder in a 1.2 V, 0.13 /spl mu/m PD/SOI technology. A performance improvement of 11.5% was obtained without significantly increasing the standby or active power. The technique was also shown to reduce the history effect in floating-body PD/SOI technology.