2nd- and 4th-order /spl Sigma//spl Delta/ modulators fabricated in 3.3 V 0.5 /spl mu/m SOS-CMOS for high-temperature applications

A /spl Sigma//spl Delta/ modulator fabricated in 0.5/spl mu/m SOS-CMOS is reported. The design incorporates two 2nd-order loops allowing reconfigurability as either a 2nd-order single loop or a 4th-order 2-2 cascade. Test results of both modulator configurations over a temperature range of 25/spl deg/C-200/spl deg/C are presented. The modulator achieves an effective resolution of 15.5 bits at 25/spl deg/C and 13.5 bits at 200/spl deg/C (both at 2KS/s). Design details pertaining to topological selection and device sizing is presented with an emphasis on temperature tolerance. Results of modulator noise analysis is presented along with techniques for improving the modulator noise performance. This paper reports the first 4th-order /spl Sigma//spl Delta/ modulator fabricated in an SOI/SOS process.