Hardening Architectures for Multiprocessor System-on-Chip

New Space missions require a short design cycle with reduced design costs and high computational capabilities. Current terrestrial commercial off-the-shelf (COTS) complex systems are the perfect candidate; however, the reliability of the devices is not granted. This work explores the reliability of complex digital systems, considering their different components. We present two different hardening architectural approaches for multiprocessor system-on-chip that combine a multicore processor and programmable logic (PL): Duplex and Duplex-triple modular redundancy (D-TMR). In the proposed hardened architectures, mitigation is accomplished for both software and hardware with system recovery capabilities that rely on the rollback process available in the dual-core processors that are running in macrosynchronized lockstep mode. The coprocessors implemented in the PL are hardened using modular redundancy techniques, and the interfaces are replicated to allow error detection and correction. Both architectures are evaluated with proton irradiation, showing a high error coverage of up to 99.3% and cross-sectional reduction of up to two orders of magnitude.