A High-Precision Low-Dropout Regulator With High Current Efficiency and Slew-Rate Enhancement

A fast-settling Low-Dropout (LDO) regulator has been presented in this paper. A new frequency compensation scheme has been proposed to ensure stability for all loading conditions without using external compensation capacitors. The new LDO regulator has been designed and simulated in a standard $0.18 \mu \mathrm{m}$ CMOS process. The simulation results show that the LDO achieves 4.42MHz and 3.6MHz unity-gain frequency for $0 \mathrm{~mA}$ and $350 \mathrm{~mA}$ of load current, respectively, while the minimum phase margin is almost 60 degrees. From the results of the simulations, it can be seen that the worst-case settling time for the load step current from $0 \mathrm{~mA}$ to $350 \mathrm{~mA}$ is $5.2 \mu \mathrm{s}$, which is reduced to $1.5 \mu \mathrm{s}$ after using a newly proposed slew-rate enhancement circuit. Also, the settling time for the load step current from $350 \mathrm{~mA}$ to $0 \mathrm{~mA}$ is almost $3 \mu \mathrm{s}$. The LDO consumes a quiescent current of 16.5 $\mu \mathrm{A}$ and the power supply rejection is $-50 \mathrm{~dB}$ at 20kHz frequency offset.