Design of Dynamic Latched Comparator Using the Offset Calibration Technique

This paper presents a dynamic latched type comparator with a positive feedback and uses wide usage of offset calibration technique for attaining the minimal offset voltage along with high speed. This is designed by using 45nm CMOS technology with offset voltage and PVT parameters verified. In order to reduce noise, delay and obtain the minimal offset voltage, this design uses extra capacitors by using a method known as digital offset calibration and obtain a value of 10.44mV at a frequency of 33MHZ at a supply voltage of 1.1V. The results are also verified with SS, SF, FS, FF process corners. It has been observed that low power consumption is obtained at SS.