Performance Analysis of Multirate Filter Structures for Signal Processing Applications

Interpolation and decimation are the two popular methods that have been adapted to perform sampling rate conversion (SRC). This paper proposes the design of cascaded stages of multirate linear phase FIR (Finite Impulse Response) Filter. Here the SRC is performed using two cascaded stages. The first stage is interpolation and the second stage is decimation. To avoid imaging problems and to eliminate aliasing problems, the FIR filter is used. Different architectures are considered for the design of multirate FIR filters which are namely polyphase, folded pipeline, and systolic array architectures, and their results are compared. The performance analysis is done in terms of area, power, and speed. It is found that the power dissipation is lesser in systolic array architecture than that of folded pipeline architecture whereas speed increases in folded pipeline architecture. The analysis and synthesis are carried out using Altera Quartus-II 10.0 and the results are reported.