Design of 10-bit 50Ms/s asynchronous logic SAR ADC

This article proposes a simple, low-power, and high-precision successive approximation analog-to-digital converter (SAR ADC). The SAR ADC designed in this article consists of three parts: a differential capacitor array, a comparator module, and a successive approximation logic module. By selecting a relatively low operating voltage and adopting a VCM-based capacitor array structure, the goal of reducing power consumption is achieved. Its high-speed characteristics are achieved through the use of asynchronous logic clock control. Based on SMIC 0.18$\mu$m-process achieves a SAR ADC with a power supply voltage of 1.8V, a sampling frequency of 50Ms/s, a significant bit of 9.9bit, and an SNDR of 61.39dB, which meets the expected design requirements.