Comparative Analysis of a Proposed Low-Power Adiabatic NOR Gate

This paper discusses the low-power adiabatic models because the power and energy consumption increase of our used devices has become significant. In this thought, the solution of using the battery has become complex as a scale-down battery means a low power supply has to be given, and the threshold voltage of the transistors has to decrease. Techniques like multi-threshold devices (MTCMOS), variable multi-threshold devices (VTCMOS), and dynamic threshold devices (DTCMOS) come forward to mitigate the high-power consumption, which results in thinner gate-oxide, gate leakage, and power dissipation. The adiabatic technique is also one of the methods for reducing power in a device where a pulsating AC voltage is used instead of a constant voltage supply. This study proposes an adiabatic circuit for a NOR gate using a 32nm LP PTM Model. The comparative study, among the proposed circuit and PFAL, IPFAL, 2n2n2p, and ECRL used industry-standard software Cadence and LTSpice. Results show outstanding performance in power and energy dissipation as well as lower propagation delay in terms of the proposed inverter circuit, which is approximately 5.61% less than the adiabatic circuit 2N2N2P at 100MHz which has the lowest propagation delay other than the proposed inverter circuit. Power dissipation is reduced up to 77% in the proposed inverter circuit compared to the 2N2N2P adiabatic inverter circuit, which provides lower power among all the adiabatic circuits used in the experiment at 25MHz frequency. Similarly, the power dissipation for the proposed NOR circuit becomes 93% less than ECRL, which shows the lowest results after the proposed circuit at 25MHz frequency.