A Comparative Analysis of FinFET and Nanosheet FET based Circuits with Geometrical Parameter Variations at sub-5 nm technology node

This work focuses on the implementation of Inverter, utilizing GAA NSFETs at the 5nm technology node and a comparison is performed having same gate length utilizing FinFETs too. Also, the DC and transient performance of inverters designed using these devices are investigated by varying gate lengths at this technology node. Furthermore, a comparison is made between the DC and transient performances of these logic gates and their counterparts implemented using FinFETs at the same technology node, where other geometric parameters are varied, considering equal effective widths. The findings indicate that scaling in both devices leads to deteriorated DC performance, although there is an improvement in delay and overshoots. Additionally, it is observed that the gain of the inverter decreases for lower gate lengths, with this effect being more pronounced in the case of FinFETs indicating that GAA NSFET is a better choice overall for DC and transient performance.