Design and Implementation of Operational Amplifiers with CMOS 180 nm Technology Node using gm/ID Methodology

This work deals with the design procedures for single stage and two stage operational amplifiers with CMOS 180 nm technology node using gm/ID methodology. The gm/ID methodology is a graphical technique for sizing the transistors to achieve the Figure of Merits and it helps to address the shortcomings of square law. The gm/ID lookup tables are generated for both PMOS and NMOS with CMOS 180 nm technology node in cadence virtuoso tool. The usage of design equations as constraints on the gm/ID lookup tables provide an efficient sizing to satisfy the Figure of Merits. The proposed methodology offers the advantage of reducing transistor sizes. In general, the gm/ID lookup table contains multiple possible values for a given combination of current, gain and gm/ID ratio and proposed methodology chooses the most appropriate value to optimize the transistor’s area in the circuit design. This helps achieve the desired gm/ID ratio while minimizing the physical space occupied by the transistor. This reduction in transistor dimensions enables overall area reduction. The proposed methodology helps to improve the Common Mode Rejection Ratio of the single stage and two stage operational amplifier. It also provides an increased differential gain in case of two stage operational amplifier. The design is validated with cadence virtuoso and the results are compared.