Approximate comparator based on Code Conversion technique for Image Processing

Approximate computing is an energy-efficient design technique applied in digital arithmetic systems that can tolerate error or quality loss. In this paper, a novel high-performance approximate comparator is proposed with less complexity and error. In this method, the input bits of the numbers are divided into sub-blocks depending on accuracy. To improve the performance each sub-block bits are converted into special code words which reduces the number of comparisons. The numerical analysis shows that the complexity is very much reduced for higher-order comparisons. To validate the proposed method 16-bit, and 32-bit comparison is implemented in Vivado 2022.1. The simulation result shows an increase in speed compared to the conventional comparator circuit with a lower error rate and lower power consumption. In 100 percent accuracy, the proposed approximate comparator has a critical path delay of 2.8nS as compared to the conventional comparator’s 4nS, indicating a 1.5 times increase in speed. The proposed comparator is applied in median filtering to remove salt and pepper noise and in visual validation it shows acceptable performance.