A new 18nm FinFET-based Programmable Logic Array type Multiplexer for High-speed and Low-Power applications

The speed and power of a circuit are the primary attributes one looks for in a design. To accompany a fast technologically driven world where usage of electronic devices is rapidly increasing, speed and power are essential for attaining desired goals. While conventional CMOS has been coping with all the demands of the industry until now, as the technology is being scaled down CMOS couldn’t keep up with the desired performance. This paper proposes an 8:1 Multiplexer with Programmable Logic Array (PLA) like architecture using FinFET type transistors; that has reduced total power dissipation and improved circuit speed. All the circuits are functionally analyzed with various supply voltages at different frequencies. The proposed PLA-type Multiplexer (PLABJ) is compared to other existing designs that use Gate logic, Transmission Gate Logic (TGL), and 2:1 Multiplexers (MUXs) respectively. All simulations have been done on Cadence Virtuoso software at 18nm FinFET technology. The delay and power dissipation, of the proposed PLABJ is found to be less by 12.7% and 11.35% than the best existing design. The corner analysis is also performed for all the designs using Cadence ADEXL. The proposed compact multiplexer is best-suitable for high-speed and low-power applications.