A Low-Power Variation-Tolerant 7T SRAM With Enhanced Read Sensing Margin for Voltage Scaling

Reducing the minimum operating voltage (Vmin) and improving the variation tolerance are the main design challenges of voltage-scalable SRAMs. This paper presents a variation-tolerant 7T SRAM with reduced data-dependent RBL leakage to enhance read sensing margin and improve Vmin without any assist techniques. The design implements a delay-tracking-based adaptive timing generation technique and an error detection circuit for PVT variation-tolerant operation and reliable dynamic voltage scaling. An 8Kb SRAM macro is implemented in 55nm CMOS technology to demonstrate our design. Post-layout simulation results show error-free full functionality down to 0.35V at an operating frequency of 202kHz. The RBL leakage current for 7T SRAM cell is improved by 2.6x and the Ion-to-Ioff ratio is improved by 2.3x compared to the conventional 8T SRAM cell. The minimum energy of 1.76pJ is achieved at 0.4V. The proposed 7T SRAM functioning as an on-chip memory in a voltage-scalable SoC is measured and demonstrate operation from 0.75V to 1.2V at 32MHz. The average power consumption for the entire chip performing 7T read and write operations decreased by 19.3% compared to that of the standard 6T SRAM at 0.75V.