Design of 2.1-4.8GHz Fractional-N Frequency Divider based on Digital Delta-Sigma Modulator and Clock Distribution Technique

The proposed fractional-N frequency divider (FD) using a digital delta-sigma modulator and clock distribution technique is designed for 5G/WiFi frequency synthesizers. The proposed FD implemented in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 $\mu$ m digital CMOS process, its active core area, and full chip size occupied 0.083 mm
²
and 0.56 mm
²
, respectively. At 4.8GHz input frequency, it dissipates 2.6mW from 1.8V supply voltage. The overall operating frequency range is 2.1GHz to 4.8GHz, with a total division ratio of 64 to 124 and a divisor resolution step of 0.25.