A 280 GHz Quadruple-Push Subharmonic Down-Conversion Mixer with Load Impedance Optimization

This paper presents the design and fabrication of a 280 GHz quadruple-push subharmonic down-conversion mixer with optimized load impedance using a 45nm CMOS-SOI. A mixer-first architecture is widely used in sub-THz band receivers because of the difficulty of achieving high gain and low NF in low noise amplifiers. Moreover, in sub-THz band mixers, the 4th harmonic mixer is utilized to reduce the chip area and the power consumption by reducing the local oscillator frequency. The proposed 4th harmonic down-conversion mixer uses the AND-gate switching topology for the mixer core and load impedance optimization to prevent degradation of the conversion gain. The proposed mixer achieved the measured conversion gain of −21.9 dB with a small chip area of 0.09 mm
²
by eliminating the bandpass filter.