A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber

A receiver bridge chip, which supports both the C-PHY version 1.1 and D-PHY version 2.0 specifications of the mobile industry processor interface (MIPI), is proposed to be used in a field-programmable gate array (FPGA)-based frame grabber supporting the MIPI camera serial interface (CSI)-2. The proposed receiver bridge chip consists of a 4-lane D-PHY receiver (RX), a 3-lane C-PHY RX, a digital logic including 8b/10b encoder, and a 3-lane 8.0 Gb/s transmitter (TX) including a clock generator. The MIPI D-PHY RX consists of four data lanes and one clock lane. Each data lane consists of a high-speed (HS) RX with an equalizer and a 1-to-8 de-serializer including a sync word detector. The MIPI C-PHY RX consists of three lanes. Each lane supporting a data rate of 2.8 Gsym/s/lane includes an HS RX, a clock recovery, a de-serializer, and a de-mapper. To serialize and output 8b/10b encoded signals for byte signals, a 1.6 GHz clock with five phases is generated from a clock generator using a charge pump phase-locked loop (CP-PLL) with an
$LC$
voltage-controlled oscillator (LCVCO). Each phase of the five-phase clock is controlled to have an even phase through a phase error calibration circuit. The proposed receiver bridge chip enables the evaluation of six camera modules with the MIPI C-PHY using only one FPGA chip. When using the MIPI D-PHY, ten camera modules can be evaluated. The proposed receiver bridge chip is implemented using a 55-nm CMOS process with a 1.2-V supply. The area of the implemented chip is 3
$\times $
3 mm. The power consumption of the MIPI D-PHY and C-PHY is 4.7 and 7.2 mW/Gb/s/lane respectively.