Variability-Aware Modeling of Power Supply Induced Jitter

This work presents a comprehensive study on the impact of variability on jitter in CMOS integrated circuits. As a case study, an analytical model of a CMOS inverter has been developed, and the input–output relationship is derived considering the effect of power supply noise, variations in design parameters due to fabrication process inaccuracies, and temperature. These parameters are taken as random variables, and the timing deviation in the transition edges of the output response has been modeled analytically. The proposed approach has been validated using numerical examples by comparing results obtained from the proposed analysis with the results obtained from the SPICE-based simulator. A couple of measurement examples and an application case study are also presented to validate the state-of-the-art investigation. The considered examples and application case study suggest the importance of the current study to ensure the timing budget of a system. The proposed approach can be used to estimate critical variability issues affecting the timing budgets of the systems.