Design of a Six-stage W-band Low-Noise Amplifier Using a 90-nm CMOS Technology

Abstract-This paper presents a W-band six-stage cascade, low-power, low-noise amplifier (LNA) implemented in a 90-nm CMOS process. The proposed LNA achieves gain improvement and broadband matching by cascading six common-source stages. To enhance both noise figure (NF) and the stability, a source degeneration inductor is employed at the first stage. The proposed W-band LNA demonstrates a maximum small-signal gain of 13 dB at 86.7 GHz, with a 3-dB bandwidth of 9.4 GHz 83.4-92.8 GHz), while consuming only a DC power consumption of 11.6 mW with a supply voltage of 1.2-V. The proposed LNA achieves a minimum noise figure of 8 dB at 89 GHz, remaining below 9 dB across a bandwidth of 86-90 GHz. Furthermore, the LNA exhibits an input 1-dB compression point $\left(\mathrm{P}_{1 \mathrm{~dB}}\right)$ of −18.8 dBm and an input third-order intercept point (IIP3) of −11.2 dBm at 89GHz. The chip size, including the RF and DC pads, is $0.73 \times 0.81 \mathrm{~mm}^{2}$.