The Chip-Level in-Plane Stress Distribution over BiCMOS Wafers

In this study, the in-plane stress distribution over BiCMOS wafers is investigated. Both analytical and finite element models are exploited to characterize the global and local stresses. By analyzing the single dies’ thicknesses and curvatures, the corresponding stress values at specific positions can be extracted. It is found that although the layout design of the die results in a few hundred N/m stresses and is the major contributor to the die stress, the process on-wafer variation, which can bring a variation of ± 50-60 N/m to the total stress, is also not negligible.