Calculation of the Worst-Case Voltage Noise for a Power Distribution Network Based on Ramp Current

With the continuous reduction of integrated circuit processing size and increasing integration density, power supply noise seriously threatens further improvement of high-speed digital system performance, which can cause jitter, latency, and even system malfunction. Power supply noise is strongly related to the design quality of the power distribution network and the activity of transient currents. In this paper, a method for estimating the worst-case voltage supply based on the ramp time of the transient current is proposed. At the same time, the worst-case current activity can also be obtained which can be used to guide the core or field programmable gate array (FPGA) design for a given power distribution network. The ramp current is first encoded and divided into segments. Then, two dynamic matrices are used to track the worst-case accumulated voltage noise and worst-case current activities. The proposed method is compared with state-of-the-art approaches showing consistent advantages in estimating the worst-case power supply noise. Its accuracy is also validated by comparing the simulated and measured data.