Timing Optimization of Pipelined ADC Based on Dynamic Comparator Latch Characteristics

This article modifies the timing of the pipeline ADC based on the latch characteristics of the dynamic comparator, which greatly reduces the requirements of the high-speed pipeline ADC for the comparator transmission delay and the setup time of the residual operational amplifier. The timing duty cycle of the pipeline ADC is modified to adopt a new system timing with 25% sampling time and 75% holding amplification time. Compared with the traditional 50% duty cycle pipeline ADC, more time can be reserved for the comparison output of the comparator and the signal establishment of the operational amplifier, which can greatly reduce the power consumption of the op-amp and provide a method for the design of low-power pipeline ADCs. Under the premise of ensuring that the linearity index of the pipeline ADC system is similar to or even better than the linearity index of the system through traditional timing, the power consumption can be reduced by about 60% at a sampling frequency of 4 MHz with a sampling accuracy of 12 bits.