A Low-power CNN Processor for Edge Devices Based on Tight Coupling of CPU and Accelerator

With the development of AIoT, edge devices are suffering from more and more power consumption brought by the CNN process of AI applications. This paper proposes a low-power CNN processor for edge devices based on the tight coupling of the CPU and accelerator to alleviate the problem. The CNN processor consists of a low-power RISC-V CPU and an accelerator, tightly coupled by the co-processor interface. Coprocessor instructions of the CPU go through the co-processor interface and transfer to the control signals of the accelerator. The accelerator has instruction-controlled logic and configuration registers, instead of accelerator self-controlled circuits, which helps to reduce power potential costs by hardware controlling circuits. By monitoring the instructions, the processor only makes relevant circuits of the executing instructions power-on, to reduce power consumption. Based on the CPU's RISC-V instruction compilation environment, the co-processor assembly instructions for the accelerator are defined, and their C language library is established. In experiments based on Xilinx FPGA, clock gating and combination logic input disabled are used to implement the power-on and power-off operations. With computation accuracy of 98.51% and more than 2000 times acceleration for CNN, the power consumption of this CNN processor is 0.348W at 16 MHz, lower than relative works, which gives a new idea of reducing power on edge devices.