Design and Verification of 1X3 Router

Routing is the method of delivering data packets from source to destination. The router is an inter-networking device used to connect two or more networks and forward packets from one networking device to another. The modules present in the toplevel design are FSM, Register, Synchronizer, and FIFO. The output ports in the router are 3, which send the packets as an output. The data packet is divided into three sections: header, payload, and parity. The packets are routed to particular ports, based on their destination address. If the destination address matches the source address, then the packet gets delivered. The functions of the router are written in Verilog HDL. The design functionality is verified using the Universal Verification Methodology (UVM) with different valid test cases. The verification helps us find the functional coverage and code coverage of the router.