Design and Optimization of a Gilbert Cell Down-Conversion Mixer for Improved Linearity, Noise Figure, and Conversion Gain

This paper discusses a design process for a balancing Noise Figure, Conversion Gain, Linearity, and Power Consumption for Gilbert cell mixer topology based on 90 nm CMOS technology utilizing the Voltage Biasing technique. The simulation run on the optimized model shows a conversion gain of 10.034 dB, an input third-order intercept point at 9.68 dBm, a noise figure of 9.51 dB, and a power consumption of 4.2 mW. The designed Gilbert cell mixer is a suitable choice for RF applications that require high conversion gain, low noise figure, low power consumption, and high linearity.