A Novel Circuit-Level Method for Hardware Trojan Detection in Digital Designs

The increased dependency on the technology also increases the possible exploitation of a device by malicious agents. The protection against the insertion of Hardware Trojans in the integrated circuits (ICs) is becoming the biggest concern in the current manufacturing processes. The functionality of a Hardware Trojan is to either modify the circuit's standard running functionality or leak any confidential information from the circuit. Hardware Trojans can be detected in both pre-silicon and post-silicon stages, but vulnerability is more in the postsilicon stage. This research aims to detect a hardware Trojan with a zero probability of getting triggered, no increase in area overhead and without activating it with the help of a golden response. A new method for hardware Trojan detection is proposed here using the power feature, RC parasitic extraction, and machine learning (ML)- based clustering techniques. It can not only detect the presence of a Hardware Trojan but also detect the nets in which it is connected. Experiments are carried out on seven ISCAS'85 and seven ISCAS'89 circuits; out of 14 circuits, results were found satisfactory in 13 circuits.