Design of Dynamic NOC based Multi-core Floating Point processing element FFT for VLSI Architecture

The paper presents dynamic on chip network (NoC) on field-programmable gate array (FPGA) for floating-point processing element (FPPE) Fast Fourier Transforms (FFTs). The aim of reducing architecture was to reduce power loss and area, on the other hand the reduction of components size produce a rise in memory & delay. Therefore, to attain limitations and for area optimization, a novel FPPE architecture design based on multi-core processor with D-NOC is proposed. The mechanism proposed not only enables graceful multi-core architecture degradation possible, but also in the omission of defective cores. The expected design is scalable in terms of performance overhead, as demonstrated by the experimental results. This makes it suitable for many-cores with more than a thousand processing cores due to its low power and high speed.